Exemplary embodiments relate to a nonvolatile memory device and, more particularly, to a read method capable of correcting error using spare cells in a nonvolatile memory device.
Recently, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and which do not require the refresh function of rewriting data at specific intervals.
FIG. 1 is a diagram showing the construction of the memory cell array of a known nonvolatile memory device. The memory cell array includes a number of memory cell blocks, but only one memory cell block is illustrated, for the sake of simplified description.
The memory cell array includes a number of memory cell blocks. Each of the memory cell blocks includes a number of strings coupled to respective bit lines BL and in parallel coupled to a common source line CSL. Each of the strings includes memory cells MC0 to MCn configured to store data, a drain select transistor DST coupled between the bit line BL and the memory cells, and a source selection transistor SST coupled between the memory cells and the common source line CSL. The gates of the drain select transistors DST of the respective strings are coupled to a drain selection line DSL. The gates of the source selection transistors SST of the respective strings are coupled to a source selection line SSL. The gates of the memory cells MC0 to MCn are coupled to respective word lines WL0 to WLn. As shown in FIG. 1, each of the word lines is called a page. An even bit line BLe and an odd bit line BLo are alternately coupled to the cell strings.
FIG. 2 is a conceptual diagram of the memory cell array of the known nonvolatile memory device. This figure shows main cells and spare cells corresponding to one page.
Referring to FIG. 2, the number of main cells 10 coupled to the even bit line is ‘n’, the number of spare cells 20 is ‘a’, the number of main cells 30 coupled to the odd bit line is ‘n’, and the number of spare cells 40 is ‘a’. Accordingly, a total number of the cells in one page are 2n+2α.
As described above, the number of spare cells 20 coupled to the even bit line is equal to the number of spare cells 40 coupled to the odd bit line. Such a design is based on the assumption that upon program, the error rate of cells coupled to the even bit line is equal to the error rate of cells coupled to the odd bit line. However, the error rate of the cells coupled to the even bit line is not equal to the error rate of the cells coupled to the odd bit line. Furthermore, in the case in which the cells coupled to the even bit line are first programmed and the cells coupled to the odd bit line are then programmed, the threshold voltage Vt of the cells coupled to the even bit line is influenced by interference generated when the cells coupled to the odd bit line are programmed. In such a case, the error rate of the cells coupled to the even bit line is higher than the error rate of the cells coupled to the odd bit line.
In the case in which as described above, the error rate of the cells coupled to the even bit line is higher than the error rate of the cells coupled to the odd bit line, more parity bits are required on the part of the even bit line when error correction code (hereinafter referred to as an ‘ECC’) processing is performed. However, if the number of spare cells 20 coupled to the even bit line is equal to the number of spare cells 40 coupled to the odd bit line as shown in FIG. 2, the parity bits stored in the spare cells 20 are insufficient when the ECC processing for the even bit line is performed, but the parity bits stored in the odd spare cells 40 remain intact when the ECC processing for the odd bit line is performed, because the same number of parity bits for the ECC processing is stored in each of the spare cells 20, 40. Accordingly, a known construction, such as that shown in FIG. 2, is a concern in that ECC processing is operated inefficiently. In the case in which when the error rate of the cells coupled to the even bit line is high, the capacity of the spare cells coupled to the even bit line is to be increased, an overall cell area is increased, resulting in increased production costs.